The present disclosure relates to a semiconductor memory device, and more particularly, to a sense amplifier power supply circuit.
Generally, an internal power voltage lower than an external power voltage is used in a memory storage and a bit line sense amplifier in order to reduce power consumption but improve reliability of a dynamic random access memory (DRAM). However, there is a limitation in that much time is required to sense a very small amount of electric charge flowing from a memory cell and convert the sensed electric charge into a complementary metal oxide semiconductor (CMOS) level.
In order to solve this limitation, a bit line sense amplifier overdriving method has been proposed. According to the bit line sense amplifier overdriving method, a sense amplifier operates with an external voltage in an initial operation until a voltage level reaches an internal voltage level, and then operates with an internal voltage.
In such a conventional method, the external power voltage VDD is used in the initial operation and then the internal voltage, i.e., a core voltage (VCORE) is used when a sensed data level reaches the internal voltage level (VREF).
FIG. 1 illustrates a circuit diagram of a conventional sense amplifier power supply circuit.
Referring to FIG. 1, the conventional sense amplifier power supply circuit develops a bit line of a sense amplifier through a driver that operates in response to a first enable signal SAP1 and a second enable signal SAP2.
As technology is advanced, a sub-hole area decreases. Therefore, there is a limitation in increasing a channel width of an SAP1/2 driver within a restricted area so as to improve RTO drivability.
As a result, low RTO drivability may affect a RAS to CAS delay time (tRCD), which is a speed parameter.
A core voltage noise affects peripheral circuits. As illustrated in FIG. 1, a core voltage level fluctuates after an overdriving operation is performed in response to the enable signal SAP1. The fluctuation of the core voltage level affects a delay circuit using the core voltage. Therefore, it is difficult to ensure a sufficient timing margin, deteriorating chip characteristics.